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features watchdog monitors sda signal (cat1161) 400khz i 2 c bus compatible 2.7v to 6.0v operation low power cmos technology 16-byte page write buffer built-in inadvertent write protection ?v cc lock out ?write protect pin, wp active high or low reset ?precision power supply voltage monitor ?5v, 3.3v and 3v systems ?five threshold voltage options 1,000,000 program/erase cycles manual reset 100 year data retention 8-pin dip or 8-pin soic commercial and industrial temperature ranges pin configuration block diagram ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice description the cat1161/2 is a complete memory and supervisory solution for microcontroller-based systems. a serial eeprom memory (16k) with hardware memory write protection, a system power supervisor with brown out protection and a watchdog timer are integrated together in low power cmos technology. memory interface is via an i 2 c bus. the 1.6-second watchdog circuit returns a system to a known good state if a software or hardware glitch halts or ?angs?the system. the cat1161 watchdog monitors the sda line, making an additional pc board trace unnecessary. the lower cost cat1162 does not have a watchdog timer. the power supply monitor and reset circuit protects memory and system controllers during power up/down and against brownout conditions. five reset threshold doc no. 3002, rev. d cat1161/2 voltages support 5v, 3.3v and 3v systems. if power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, asic or peripherals from operating. reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. with both active high and low reset signals, interface to microcontrollers and other ics is simple. in addition, a reset pin can be used as a debounced input for push-button manual reset capability. the cat1161/2 memory features a 16-byte page. in addition, hardware data protection is provided by a write protect pin wp and by a v cc sense circuit that prevents writes to memory whenever v cc falls below the reset threshold or until v cc reaches the reset threshold during power up. available packages include an 8-pin dip and a surface mount, 8-pin so package. cat1161/2 (16k) supervisory circuits with i 2 c serial cmos eeprom, precision reset controller and watchdog timer part dash minimum maximum number threshold threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 16k d out ack sense amps shift registers control logic word address buffers start/stop logic eeprom v cc external load column decoders xdec data in storage high voltage/ timing control gnd wp sda reset controller precision vcc monitor state counters slave address comparators scl reset reset watchdog only for cat1161 dc = do not connect dc v cc reset scl sda reset wp gnd
2 cat1161/2 doc. no. 3002, rev. d d.c. operating characteristics v cc = +2.7v to +6.0v, unless otherwise specified. symbol parameter test conditions min typ max units i cc power supply current f scl = 100 khz 3 ma i sb standby current v cc = 3.3v 40 a v cc = 5 50 a i li input leakage current v in = g nd or v cc 2 a i lo output leakage current v in = g nd or v cc 10 a v il input low voltage -1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage (sda) i ol = 3 ma, v cc = 3.0v 0.4 v absolute maximum ratings temperature under bias ................. ?5 c to +125 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to ground (1) ............ ?.0v to +v cc +2.0v v cc with respect to ground ............... ?.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. reliability characteristics symbol parameter reference test method min max units n end (3) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (3) data retention mil-std-883, test method 1008 100 years v zap (3) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (3)(4) latch-up jedec standard 17 100 ma note: (1) the minimum dc input voltage is ?.5v. during transitions, inputs may undershoot to ?.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from ?v to v cc +1v. pin functions pin no. pin name function 1 dc do not connect 2 reset active low reset i/o 3 wp write protect 4 gnd ground 5 sda serial data/address 6 scl clock input 7 reset active high reset i/o 8v cc power supply
3 cat1161/2 doc no. 3002, rev. d capacitance t a = 25?c, f = 1.0 mhz, v cc = 5v symbol test conditions max units c i/o (1) input/output capacitance (sda) v i/o = 0v 8 pf c in (1) input capacitance (scl) v in = 0v 6 pf v cc = 2.7v - 6v v cc = 4.5v - 5.5v symbol parameter min max min max units f scl clock frequency 100 400 khz t i (1) noise suppresion time 200 200 ns constant at scl, sda inputs t aa slc low to sda data out 3.5 1 s and ack out t buf (1) time the bus must be free before 4.7 1.2 s a new transmission can start t hd:sta start condition hold time 4 0.6 s t low clock low period 4.7 1.2 s t high clock high period 4 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 50 50 ns t r (1) sda and scl rise time 1 0.3 s t f (1) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t dh data out hold time 100 100 ns a.c. characteristics v cc =2.7v to 6.0v unless otherwise specified. output load is 1 ttl gate and 100pf. power-up timing (1)(2) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specific operation can be initiated. write cycle limits symbol parameter min typ max units t wr write cycle time 10 ms the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle . during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its sla ve address.
4 cat1161/2 doc. no. 3002, rev. d reset circuit characteristics symbol parameter min typ max units t glitch glitch reject pulse width 100 ns v rt reset threshold hystersis 15 mv v olrs reset output low voltage (i olrs =1ma) 0.4 v v ohrs reset output high voltage v cc -0.75 v reset threshold (v cc =5v) 4.50 4.75 (cat1161/2-45) reset threshold (v cc =5v) 4.25 4.50 (cat1161/2-42) reset threshold (v cc =3.3v) 3.00 3.15 (cat1161/2-30) reset threshold (v cc =3.3v) 2.85 3.00 (cat1161/2-28) reset threshold (v cc =3v) 2.55 2.70 (cat1161/2-25) t purst power-up reset timeout 130 270 ms twp watchdog period 1.6 sec t rpd v th to reset output delay 5 s v rvalid reset output valid 1 v v th v
5 cat1161/2 doc no. 3002, rev. d pin descriptions wp: write protect if the pin is tied to v cc the entire memory array becomes write protected (read only). when the pin is tied to gnd or left floating normal read/write operations are allowed to the device. reset/ reset reset reset reset reset : reset i/o these are open drain pins and can be used as reset trigger inputs. by forcing a reset condition on the pins the device will initiate and maintain a reset condition. the reset pin must be connected through a pull- down resistor, and the reset pin must be connected through a pull-up resistor. sda: serial data address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. if there is no transition on the sda for more than 1.6 seconds, the watchdog timer times out. scl: serial clock serial clock input. device operation reset controller description the cat1161/2 precision reset controller ensures correct system operation during brownout and power up/down conditions. it is configured with open drain reset outputs. during power-up, the reset outputs remain active until v cc reaches the v th threshold and will continue driving the outputs for approximately 200ms (t purst ) after reaching v th . after the t purst timeout interval, the device will cease to drive the reset outputs. at this point the reset outputs will be pulled up or down by their respective pull up/down resistors. during power-down, the reset outputs will be active when v cc falls below v th . the reset outputs will be valid so long as v cc is >1.0v (v rvalid ). the reset pins are i/os; therefore, the cat1161/2 can act as a signal conditioning circuit for an externally applied manual reset. the inputs are edge triggered; that is, the reset input in the cat1161/2 will initiate a reset timeout after detecting a low to high transition and the reset input will initiate a reset timeout after detecting a high to low transition. watchdog timer the watchdog timer provides an independent protection for microcontrollers. during a system failure, the cat1161will respond with a reset signal after a time-out interval of 1.6 seconds for a lack of activity. the cat1161 is designed with the watchdog timer feature on the sda input. if the microcontroller does not toggle the sda input pin within 1.6 seconds, the watchdog timer times out. this will generate a reset condition on reset outputs. the watchdog timer is cleared by any transition on sda. as long as the reset signal is asserted, the watchdog timer will not count and will stay cleared. the cat1162 does not have a watchdog. figure 1. reset output timing glitch t v cc purst t purst t rpd t rvalid v v th reset reset rpd t
6 cat1161/2 doc. no. 3002, rev. d falls below (power down) vth or until v cc reaches the reset threshold (power up) v th . any attempt to access the internal eeprom is not recognized and an ack will not be sent on the sda line when reset or reset is active. reset threshold voltage the cat1161/2 is offered with five reset threshold voltage ranges. they are 4.50-4.75v, 4.25-4.50v, 3.00- 3.15v, 2.85-3.00v and 2.55-2.70v. hardware data protection the cat1161/2 is designed with the following hardware data protection features to provide a high degree of data integrity. (1) the cat1161/2 features a wp pin. when the wp pin is tied high the entire memory array becomes write protected (read only). (2) the v cc sense provides write protection when v cc falls below the reset threshold value (vth). the v cc lock out inhibits writes to the serial eeprom whenever v cc t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh figure 2. bus timing t wr stop condition start condition address ack 8th bit byte n scl sda figure 3. write cycle timing start bit sda stop bit scl figure 4. start/stop timing
7 cat1161/2 doc no. 3002, rev. d functional description the cat1161/2 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat1161/2 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the master begins a transmission by sending a start condition. the master sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 1010. the next three bits (figure 6) define memory addressing. for the cat1161/162 the three bits define higher order bits. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat1161/2 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat1161/2 then performs a read or write operation depending on the r/ w bit. acknowledge 1 start scl from master 89 data output from transmitter data output from receiver figure 5. acknowledge timing 1 0 1 0 a10 a9 a8 r/w 24c163 figure 6. slave address bits **a8, a9 and a10 correspond to the address of the memory array address word. cat cat1161/2
8 cat1161/2 doc. no. 3002, rev. d acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat1161/2 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. when the cat1161/2 begins a read mode it transmits 8 bits of data, releases the sda line and monitors the line for an acknowledge. once it receives this acknowledge, the cat1161/2 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends a 8-bit address that is to be written into the address pointers of the cat1161/2. after receiving another acknowledge from the slave, the master device transmits the data to be written into the addressed memory location. the cat1161/2 acknowledges once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to non-volatile memory. while the cycle is in progress, the device will not respond to any request from the master device. page write the cat1161/2 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to 15 additional bytes. after each byte has been transmitted, the cat1161/2 will respond with an acknowledge and internally increment the lower order address bits by one. the high order bits remain unchanged. if the master transmits more than 16 bytes before sending the stop condition, the address counter wraps around, and previously transmitted data will be overwritten. when all 16 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the cat1161/2 in a single write cycle. byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t figure 7. byte write timing figure 8. page write timing bus activity: master sda line data n+15 byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address
9 cat1161/2 doc no. 3002, rev. d acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host s write opration, the cat1161/2 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the cat1161/2 is still busy with the write operation, no ack will be returned. if a write operation has completed, an ack will be returned and the host can then proceed with the next read or write operation. write protection the write protection feature allows the user to protect against inadvertent memory array programming. if the wp pin is tied to v cc , the entire memory array is protected and becomes read only. the cat1161/2 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device s failure to send an acknowledge after the first byte of data is received. read operations the read operation for the cat1161/2 is initiated in the same manner as the write operation with one exception, that r/ w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. scl sda 8th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t figure 9. immediate address read timing
10 cat1161/2 doc. no. 3002, rev. d immediate/current address read the cat1161/2 address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n+1. for all devices, n=e=2047. the counter will wrap around to zero and continue to clock out valid data for the 16k devices. after the cat1161/ 2 receives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. the master device does not send an acknowledge, but will generate a stop condition. selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte addresses of the location it wishes to read. after the cat1161/2 acknowledges, the master device sends the start condition and the slave address again, this time with the r/ w bit set to one. the cat1161/2 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat1161/2 sends the inital 8-bit byte requested, the master will responds with an acknowledge which tells the device it requires more data. the cat1161/2 will continue to output an 8-bit byte for each acknowledge, thus sending the stop condition. the data being transmitted from the cat1161/2 is outputted sequentially with data from address n followed by data from address n+1. the read operation address counter increments all of the cat1161/2 address bits so that the entire memory array can be read during one operation. if more than e (where e=2047 for the cat1161/162) bytes are read out, the counter will wrap around and continue to clock out data bytes. manual reset operation the cat116x reset or reset pin can also be used as a manual reset input. only the active edge of the manual reset input is internally sensed. the positive edge is sensed if reset is used as a manual reset input and the negative edge is sensed if reset is used as a manual reset input. an internal counter starts a 200 ms count. during this time, the complementary reset output will be kept in the active state. if the manual reset input is forced active for more than 200 ms, the complementary reset output will switch back to the non active state after the 200 ms expired, regardless for how long the manual reset input is forced active. the embedded eeprom is disabled as long as a reset condition is maintained on any reset pin. if the external forced reset/ reset is longer than internal controlled time-out period, tpurst, the memory will not respond with an acknowledge for any access as long as the manual reset input is active. slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t figure 10. selective read timing
11 cat1161/2 doc no. 3002, rev. d bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address figure 11. sequential read timing note: (1) the device used in the above example is a cat1162ji-30te13 (16k i 2 c memory, soic, industrial temperature, 3.0-3.15v reset threshold voltage, tape and reel) ordering information 1162 temperature range blank = commercial (0? to 70?c) i = industrial (-40? to 85?c) prefix device # suffix j i te13 product number 1161: 16k 1162: 16k tape & reel te13: 2000/reel package p: pdip j: soic (jedec) -30 cat reset threshold voltage 45: 4.5-4.75v 42: 4.25-4.5v 30: 3.0-3.15v 28: 2.85-3.0v 25: 2.55-2.7v optional company id
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 3002 revison: d issue date: 03/29/02 type: final

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